1. Field of the Invention
The present invention relates generally to a decoding apparatus and, more particularly, to a decoder for use with digital signal reproducing equipment used for reproducing a digital information signal, such as a digital audio signal, a digital video signal, or the like.
2. Description of the Background
As an error correction code in the case of recording/reproducing a digital audio signal, such as a PCM signal, by a pair of rotary heads there is frequently used a so-called block completion type product code in which the PCM signals to be recorded/reproduced by one rotary head are arranged in a matrix form. In the block completion code the coding of a first error correction code, referred to as C1 code, is performed for the PCM signals arranged in the vertical or column direction of this matrix arrangement. The coding of a second error correction code, referred to as C2 code, is executed for the PCM signals arranged in the lateral or row direction of the matrix arrangement. The PCM signals that have been subjected to the coding of those two error correction codes and the vertically arranged check symbols of the respective error correction codes C1 and C2 are then recorded.
On the reproduction side, the C1 decoding of the error correction code C1 is performed after the writing of reproduced data into a buffer memory, and the C2 decoding of the error correction code C2 is then executed.
In a product code, the error correction capability increases with increased numbers of the C1 decoding and C2 decoding. Despite the fact that the correction capability for random error is improved with the increased number of decodings, the C1 decoding and the C2 decoding are usually performed only once. This is because the time available for decoding is limited. It has been proposed that the time used for decoding be lengthened by improving the processing speed by using an increased operational clock frequency in the processor for decoding. Nevertheless, there are the problems of access time for a buffer memory and of increased power consumption. For this reason, simply raising the operational clock frequency of the processor is not a desirable or workable solution.